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HIP0060
July 1997
1.5A, 50V Quad Low Side Power Driver with Serial Bus Control and Fault Protection
Description
The HIP0060 is a 5V logic controlled Quad Low Side Power Driver. The outputs are individually protected for over-current (OC), over-temperature (OT) and over-voltage (OV). If an OC short circuit in the output load is sensed (IS) in one output power driver, that output current will be independently limited while the other outputs remain in operation. Over-current is limited by direct gate feedback. Over-voltage protection is provided by a drain-to-gate zener diode that clamps inductive switching pulses. The output drivers are individually controlled through a Gate Control Latch. Temperature is sensed at each output. If a thermal fault exists, a status flag is set and the output is latched off. Open-load (OL) and over-temperature (OT) faults sets a status flag bit as diagnostic output to the SPI bus. For all fault bits (8), an ORed one-shot interrupt signal is output to the INT pin. An RST reset clears the fault flags and disables all outputs while active. The Serial Peripheral Interface (SPI) bus pins are the Serial Input (SI), Serial Output (SO), Serial Data Clock (SCK) and the Chip Select (CS). The HIP0060 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly suited for driving lamps, relays, and solenoids in applications where low operating power, high breakdown voltage, and higher output current at high temperatures is required.
Features
* Quad NDMOS Output Drivers in a High Voltage Power BiMOS Process * Over-Stress Protection - Each Output - Over-Current Limiting . . . . . . . . . . . . . . . . . .1.5A Min - Internal Zener Drain-to-Gate Over-Voltage Clamp Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Typ - Thermal Shutdown Protection - Open-Load Detection * Low Quiescent Current . . . . . . . . . . . . . . . . 10mA Max * Serial Diagnostic Link with SPI Bus * Diagnostic Interrupt Fault Flag * 5V CMOS Logic Input Control * Common Reset for Fault Bits and Output Drivers * Ambient Operating Temperature Range. . . . . . . . . . . . . . . . -40oC to 125oC
Applications
* Automotive and Industrial Systems * Fuel Injection Drivers * Solenoids, Relays and Lamp Drivers * Logic and P Controlled Drivers * Robotic Controls
Ordering Information
PART NUMBER HIP0060AB TEMP. RANGE (oC) -40 to 125 PACKAGE 24 Ld SOIC PKG. NO. M24.3
Pinout
HIP0060 (SOIC) TOP VIEW
Block Diagram
CHANNEL A (1 OF 4) VDD +5V GATE CONTROL LATCH + O.T. BIT RST SCK SI SO CS 8-BIT SPI (SERIAL DIAG. REG) INT O.L. BIT OPEN LOAD DETECTOR OVER TEMP. DETECTOR OUTA
GND INT INA OUTA GND GND GND GND OUTB
1 2 3 4 5 6 7 8 9
24 VDD 23 RST 22 IND 21 OUTD 20 GND 19 GND 18 GND 17 GND 16 OUTC 15 INC 14 SO 13 SCK INA
OVER CURRENT LIMIT
IS
INB 10 SI 11 CS 12
2 2 2 2 2 2
8 ORed O.T./O.L. FAULT INPUTS, ONE-SHOT MULTI OUTPUT
TO B, C, D
FROM B, C, D
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4045
1
HIP0060
Absolute Maximum Ratings
Max Output Voltage, VOUT (Note 2) . . . . . . . . . . . . . . . . . . . . . VOC Max Output Load Current, ILOAD (Per Output, Note 3) . . . . . . . . ICL Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Logic Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 4) JA (oC/W) SOIC - PC Board Mount, Min. Copper . . . . . . . . . . 60 SOIC - PC Board Mount, 2 sq. in. Copper . . . . . . . . 35 Maximum Storage Temperature Range -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC Junction Temperature Range . . . . . . . . . . . . . . . . -40oC to 150oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns on the MOSFET; holding the Drain at the Output Clamp voltage VOC. 3. The output drive is protected by an internal current limit. The ICL over-current limiting threshold parameter specification defines the maximum current. The maximum current with all outputs ON may be further limited by dissipation. 4. Device dissipation is based on thermal resistance capability of the package in a normal operating environment. The junction to ambient thermal resistance of 60oC/W is defined here as a PC Board mounted device with minimal copper. With approximately 2 square inches of copper area as a heat sink, it is practical to achieve 35oC/W thermal resistance. Further reduction in the thermal resistance can be achieved with additional PC Board Copper ground area or an external heat sink structure next to the ground leads at the center of the package.
Electrical Specifications
PARAMETER
VDD = 4.5V to 5.5V, VSS = 0V, TA = -40oC to 125oC; Unless Otherwise Specified SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUTS DRIVERS (DR0 TO DR7) Output Channel Resistance Over-Current Limiting Threshold Output Clamping Voltage Output Clamping Energy Output OFF Leakage Current Open-Load Fault Threshold Output Rise Time Output Fall Time Turn-On Delay Turn-Off Delay POWER SUPPLY Power On Reset Threshold VDD Logic Supply Current VDD(POR) IDD All Outputs ON or OFF 3.2 4.4 10 V mA rDSON ICL VOC EOC ILK ROLD tR tF tON tOFF 1ms Single Pulse Width, TA = 25oC, (Refer to Figure 3 for SOA Limits). VOUT = 14.5V VOUT = 14.5V, Output Off RL = 30, VOUT = 14.5V RL = 30, VOUT = 14.5V RL = 30, VOUT = 14.5V RL = 30, VOUT = 14.5V 4 1 1 180 200 12 12 12 12 A k s s s s IOUT = 0.5A 1.5 40 50 85 0.8 3.5 60 A V mJ
LOGIC INPUTS (INx, SI, SCK, RST, CS) High Level Input Voltage Low Level Input Voltage Input Hysteresis High Output Voltage, SO, INT Low Output Voltage, SO Input Pull-Down Current, INx Reset Input Pull-Up Current, RST VIH VIL VILHYS V OL V OH IINPD IRPU Current Sink = 1.6mA Current Source = -0.8mA 0.7xVDD 0.8 VDD -0.8 75 20 0.2xVDD 0.4 250 120 V V V V V A A
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HIP0060
Electrical Specifications
PARAMETER DIAGNOSTIC Pulse Width, INT Fault Response Time t INT tFAULT 3 25 16 s s VDD = 4.5V to 5.5V, VSS = 0V, TA = -40oC to 125oC; Unless Otherwise Specified (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS
OVER-TEMPERATURE PROTECTION Over-Temperature Shutdown TSD 160 oC
SERIAL PERIPHERAL INTERFACE TIMING (Capacitance Each Pin, CL = 200pF) SCK Period SCK Clock High/Low Time SCK Rise/Fall Time Enable Lead/Lag Time Output Data Valid Time Data Setup Time Disable Time tCYC tWSCKH, tWSCKL trSCK, tfSCK tLEAD, tLAG tV tSU tDIS 500 200 250 30 170 30 250 ns ns ns ns ns ns ns
Description of Diagnostics
OC (Over-Current) Fault Mode In a short circuit or over-current fault condition when an output is switched on, the output current is limited to the ICL maximum as defined in the Electrical Specifications. An OC fault condition does not shutdown the output. The current is sensed and feedback is directed to the gate of the MOS Output Driver. The gate voltage is reduced to maintained the specified level of current limiting. In this mode, the drain voltage will increase and cause increased dissipation. OT (Over-Temperature) Fault Mode Under a high dissipation over-temperature fault condition, the output temperature is detected and compared to a preset threshold level. When the OT threshold is exceeded, thermal shutdown for that output occurs. The Gate Control Latch drive to the output is switched off and a status flag (the OT Bit) for the fault is set. The output shutdown action is independent of the IN input state. However, the Gate Control Latch and OL Bit will be reset on the next rising edge of the IN input and, if the fault still exists, the shutdown action will repeat. Diagnostic action for an OT fault includes feedback of the fault status to the Serial Diagnostic Register for a SPI bus data output. Also, as shown in the Block Diagram, the OT fault status bit information is ORed into a one-shot that drives an open drain to provide an INT interrupt signal output. The INT output has a specified timing from the one-shot multi and is defined in the Electrical Specifications as t INT.
OL (Open-Load) Fault Mode An open-load fault mode sequence consists of setting a status flag (the OL Bit) when an output open load condition is detected. If the output impedance is greater than a preset threshold, as detected when the input is off; the status bit is set. The OL Bit is reset on the next falling edge of the IN input signal. The off-on detection sequence will repeat as long as the output impedance is higher than the detection threshold, as detected in the off state. Diagnostic action for an OL fault mode differs from the OT fault mode by not forcing an output shutdown through the Gate Controlled Latch. Also, because the OL fault is detected in the off state, the status flag is reset on the falling edge of the input instead of the rising edge. The OL output information to the Serial Diagnostic Register and the INT pin is the same as the OT fault mode action. ORed Fault Bits It is important to note that the trigger input to the one-shot is locked-out for the t INT duration and any fault that may have occurred in the t INT window will not be displayed at the INT output. However, all 8 fault bits may still be read as data from the SO output when clock by the SCK input. The INT fault output is provided as an interrupt signal to flag the immediate occurrence of a fault and take appropriate action as defined by the microcontroller to the SPI bus and the users programming. The INT fault output may be ORed with other ICs to provide a system microcontroller interrupt to indicate the presence of a fault.
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HIP0060
Serial Diagnostic Link A serial diagnostic link via the SPI bus provides the means to clock fault data in and out of the fault register to the microcontroller. When the microcontroller receives an INT interrupt signal, data is clocked from the Serial Diagnostic Register to determine what fault bit has been set. Appropriate action for the fault may then be taken, as defined by the programming of the microcontroller. Serial Diagnostic Register Fault bits consist of one OT bit and one OL bit for each switching channel (A, B, C and D). Data is transferred out of SO MSB first on the rising edge of SCK after CS goes low. Data is shifted into the input shift register on the falling edge of SCK. The defined order of the DO0 to DO7 fault bits is as follows:
BIT DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 NAME OTA OTB OTC OTD OLA OLB OLC OLD CONDITION REQUIRED TO SET BIT OT in Output Driver A, TJ TLIM OT in Output Driver B, TJ TLIM OT in Output Driver C, TJ TLIM OT in Output Driver D, TJ TLIM OL in Output Driver A, OFF Load > ROLD OL in Output Driver B, OFF Load > ROLD OL in Output Driver C, OFF Load > ROLD OL in Output Driver D, OFF Load > ROLD
HIP0060 devices may be linked in cascade for the purposes of SPI control. Serial data is clocked in and out of each HIP0060 and then back to the host microcontroller. All linked devices have a common control sequence. When CS goes low, fault data is shifted to the Serial Diagnostic Register. SCK must be low when CS goes low. Also, when CS goes low, SO changes from a three-state to a low state and remains low until SCK goes high. Serial data is transferred by SCK. After the serial data is transferred, SCK must remain low as CS goes high. The serial data transfer must be a continuous sequence while CS is low. Serial Peripheral Interface The Serial Peripheral Interface (SPI) bus is system controlled by a host micro. The SPI bus controls the Serial Diagnostic Link with the CS (Chip Select), SCK, SI, SO and RST (Reset) lines. Figures 4 and 5 define the timing and protocol for the bus. Reset Operation The RST input is an active low reset input. When RST is low, the internal diagnostic flags are cleared but not the shift register. When RST is low, all outputs and output switches are disabled. To clear the shift register, CS is switched from high to low during or after a reset while there are no active faults, jamming data from the cleared fault flags into the shift registor. The RST input has an internal pull-up to sustain a logic high when floating. The VDD input is the power supply to the 5V logic and the POR function. When the VDD is less than the VDD(POR) threshold, the output drivers are shutoff. To insure that the diagnostic link shift register is correct after VDD is less than VDD(POR), a manual reset must be executed.
4.7k INT
VDD +5V OUTA
SOLENOID
RST OUTB INA INB INC IND HIP0060 OUTC
RELAY
VBATT
LAMP OUTD M MOTOR VBATT
FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR MOTORS OR STEPPER MOTORS
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HIP0060
+5V 4.7k RST INA OUTB 50 5V, 100s 2% DUTY CYCLE FUNCTION GEN. IND INT INB INC HIP0060 (TIMING TEST CIRCUIT) OUTC 30 VDD
+14.5V 30
4.7k
OUTA
30
OUTD GND
30
5V VIN 3V 0V tON tr 14.5V VOUT 0V 10% 10% 90% 1V tOFF tf 90%
FIGURE 2. INPUT TO OUTPUT SWITCHING TIME DIAGRAM FOR EACH SWITCHING CHANNEL. THE CONDITIONS SHOWN REFER TO THE TIMING TEST CIRCUIT
10000
ENERGY (mJ)
1000
100
SAFE OPERATING AREA BELOW LINE
10 0.1
1 TIME (ms)
10
100
FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, TA = 25oC
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HIP0060 Timing Diagrams
CS
SCK (CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 4. DATA AND CLOCK TIMING DIAGRAM
CS tLEAD tCYC tfSCK trSCK tLAG
SCK
tWSCKH tWSCKL tSU
SI
DI7
DI6
DI1
D10
tDIS SO (THREE-STATE) tV DO7 DO6 DO1 DO0
FIGURE 5. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET. REFER TO THE ELECTRICAL SPECIFICATION FOR THE HIGH AND LOW INPUT AND OUTPUT THRESHOLD LEVELS SHOWN FOR TIMING REFERENCE
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HIP0060 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact
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